Organic electroluminescent (hereinafter abbreviated to EL) elements are known as self-luminous elements used to implement thin, low-power consuming display devices. A display device and its drive circuit using EL elements are described in Japanese Patent Laid-Open No. 2001-42821.
FIG. 1 shows schematic configuration of this EL element. As shown in the figure, the EL element is made by laminating a transparent substrate 100 such as a glass substrate on which a transparent electrode 101 is formed; at least one organic functional layer 102 composed of an electron transport layer, luminescent layer, and hole transport layer; and a metal electrode 103.
FIG. 2 is an equivalent circuit diagram showing characteristics of the EL element electrically. The EL element shown in the figure can be replaced by a capacitive component C and a component E which has properties of a diode and is coupled in parallel with the capacitive component.
If a direct current is passed between the transparent electrode 101 and metal electrode 103 with a positive voltage applied to the anode (+pole) of the transparent electrode 101 and a negative voltage applied to the cathode (−pole) of the metal electrode 103, electric charge is accumulated in the capacitive component C. When quantity of the charge exceeds the level of an inherent barrier voltage or luminescence threshold voltage of the EL element, a current starts to flow from an electrode (the anode of the diode component E) to the organic functional layer which carries the luminescent layer and the organic functional layer 102 (see FIG. 1) emits light with intensity proportional to the current.
FIG. 3 shows schematic configuration of an EL display device which displays images using a EL display panel consisting of a plurality of the EL elements arranged in a matrix. In the figure, cathode lines (lines connected to the metal electrode) B1 to Bn carrying a first display line to n-th display line, respectively, and m anode lines (lines connected to the transparent electrode) A1 to Am intersecting the cathode lines B1 to Bn are formed on an ELDP 10, i.e., an EL display panel. EL elements E11 to Enm with the above described configuration are formed at respective intersections (n×m intersections) of the cathode lines B1 to Bn and anode lines A1 to Am. In addition, each of the EL elements E11 to Enm corresponds to each pixel of the ELDP 10.
A luminescence control circuit 1 converts one screen (n rows×m columns) of input image data into pixel data D11 to Dnm corresponding to the pixels of the ELDP 10, i.e., the EL elements E11 to Enm, and supplies sequentially them row by row to an anode line drive circuit 2 as shown in FIG. 4. For example, pixel data D11 to D1m consist of m data bits which specify whether the respective EL elements E11 to E1m belonging to the first display line of the ELDP 10 should emit light. Each of them indicates “luminescence” when it is at logic “1,” and “non-luminescence” when it is at logic “0.”
The luminescence control circuit 1 supplies a cathode line selection control signal to a cathode line drive circuit 3 in synchronization with row-by-row supply of pixel data as shown in FIG. 4 to scan the first display line to n-th display line of the ELDP 10 in sequence. First, the anode line drive circuit 2 extracts all the data bits with a logic “1” which specifies “luminescence” from the m data bits in the pixel data group. Then, it selects all the anode lines which belong to the “columns” corresponding to the extracted data bits from the anode lines A1 to Am, and connects a constant current source and supplies a predetermined pixel drive current i only to the selected anode lines.
The cathode line drive circuit 3 selects the cathode line—only one cathode line at a time—which corresponds to the display line indicated by the cathode line selection control signal from among the cathode lines B1 to Bn and connects it to ground potential while applying a predetermined high potential Vcc to each of the other cathode lines. The high potential Vcc is set approximately equal to the voltage (voltage determined based on quantity of charge of a parasitic capacitance C) across a given EL element which is emitting light of desired luminance.
In this case, a light emission drive current flows between the “columns” connected to the constant current source by the anode line drive circuit 2 and the display lines set to the ground potential by the cathode line drive circuit 3. The EL elements formed at the intersections of the display lines and “columns” emit light according to the light emission drive current. On the other hand, since no current flows between the display lines set to the high potential Vcc by the cathode line drive circuit 3 and “columns” connected to the constant current source, the EL elements formed at their intersections remain non-luminescent.
As the above operations are performed based on the pixel data D11 to D1m, D21 to D2m, . . . , and Dn1 to Dnm, a screen of the ELDP 10 displays one field of light emission pattern, i.e., an image, according to the input image data.
By the way, recently, for implementation of big-screen display panels, it has become necessary to improve screen resolution by increasing the number of display lines, i.e., the cathode lines B, as well as the number of anode lines A. Thus as the number of cathode lines B and anode lines A increase, so do the scale of the anode line drive circuit 2 and the cathode line drive circuit 3. Therefore, it is feared that when both the circuits are implemented as integrated circuits, increased chip area will result in lower yields. In this connection, it is conceivable to construct the anode line drive circuit 2 and the cathode line drive circuit 3 each from a plurality of IC chips.
For example, it is conceivable to construct the anode line drive circuit 2 from two IC chips 2a and 2b as shown in FIG. 5. When the anode line drive circuit 2 is constructed from the two IC chips 2a and 2b in this way, anode lines A1 to An will be driven by the IC chip 2a and anode lines AN+1 to Am will be driven by the IC chip 2b as shown in FIG. 6. Incidentally, in FIG. 6, current outputs to the pixel elements, i.e., channel numbers for drive outputs, are denoted by “1” to “N−1,” “N,” “N+1,” “N+2” to “m.”
However, if the anode line drive circuit 2 is constructed from a plurality of IC chips as shown in FIG. 6, manufacturing variations and the like may cause differences among IC chips in the value of the light emission drive current to be supplied to the anode lines. Therefore the differences in the light emission drive current will produce areas with different luminance on the screen of the ELDP 10 and the stepwise change will consequently impair image quality especially on boundaries between these areas.
A technique for solving this problem is described in Japanese Patent Laid-Open No. 2001-42827.
FIG. 7 shows schematic configuration of an EL display device described in the Japanese patent. In the figure, the IC chip 2a functions as a first anode line drive circuit 210 while the IC chip 2b functions as a second anode line drive circuit 220. Cathode lines (lines connected to a metal electrode) B1to Bn carrying a first display line to n-th display line, respectively, and 2m anode lines (lines connected to a transparent electrode) A1 to A2m intersecting the cathode lines B1 to Bn are formed on an ELDP 10′, i.e., an EL display panel. EL elements E1,1 to En,2m with the configuration shown in FIG. 1 are formed at respective intersections of the cathode lines B1 to Bn and anode lines A1 to A2m. Each of the EL elements E1,1 to En,2m corresponds to each pixel of the ELDP 10′.
A luminescence control circuit 1′ supplies a cathode line selection control signal to a cathode line drive circuit 3 as shown in FIG. 8 to scan the first display line to n-th display line of the ELDP 10′ in sequence. The cathode line drive circuit 3 selects the cathode line—only one cathode line at a time—which corresponds to the display line indicated by the cathode line selection control signal from among the cathode lines B1 to Bn of the ELDP 10′ and connects it to ground potential while applying a predetermined high potential Vcc to each of the other cathode lines.
Also, the luminescence control circuit 1′ converts one screen (n rows×2m columns) of input image data into pixel data D1,1 to Dn,2m corresponding to the pixels of the ELDP 10′, i.e., the EL elements E1,1 to En,2m, and divides the pixel data into those belonging to the first to m-th columns and those belonging to the (m+1)-th to 2m-th columns. Then, the luminescence control circuit 1′ groups the pixel data belonging to the first to m-th columns by display line and supplies the resulting pixel data D1,1 to D1,m, D2,1 to D2,m, D3,1 to D3,m, . . . , and Dn,1 to Dn,m one after another as first drive data GA1-m to the first anode line drive circuit 210 as shown in FIG. 8. At the same time it groups the pixel data belonging to the (m+1)-th to 2m-th columns by display line and supplies the resulting pixel data D1,m+1to D1,2m, D2,m+1 to D2,2m, D3,m+1 to D3,2m, . . . , and Dn,m+1 to Dn,2m one after another as second drive data GB1-m to the second anode line drive circuit 220 as shown in FIG. 8.
The first drive data GA1-m and second drive data GB1-m are supplied one after another to the first anode line drive circuit 210 and second anode line drive circuit 220, respectively, in synchronization with the scan line selection control signal as shown in FIG. 8. The first drive data GA1-m here consist of m data bits which specify whether the respective m EL elements belonging to the first to m-th columns of each display line of the ELDP 10′ should emit light. Similarly, the second drive data GB1-m consist of m data bits which specify whether the respective m EL elements belonging to the (m+1)-th to 2m-th columns of each display line of the ELDP 10′ should emit light. For example, each of the data bits indicates luminescence when it is at logic “1,” and non-luminescence when it is at logic “0.”
FIG. 9 shows internal configuration of drive circuits, namely, the first anode line drive circuit 210 and second anode line drive circuit 220. The first anode line drive circuit 210 and second anode line drive circuit 220 are constructed in different two IC chips (see FIG. 5). In FIG. 9, the first anode line drive circuit 210 comprises a reference current control circuit RC, a control current output circuit CO, and a switch block SB as well as transistors Q1 to Qm and resistors R1 to Rm serving as m current drive sources.
The emitter of a transistor Qb in the reference current control circuit RC is connected with a predetermined pixel drive voltage VHE via a resistor Rr while the base and collector are connected with the collector of a transistor Qa. A predetermined reference voltage VREF and emitter potential of the transistor Qa are fed into an operational amplifier OP. Output potential of the operational amplifier OP is fed into the base of the transistor Qa. The emitter of the transistor Qa is connected to ground potential via a resistor Rp. With the above configuration, a reference current IREF (=VREF/Rp) flows between the collector and emitter of the transistor Qa.
The pixel drive voltage VHE is applied to the emitters of the transistors Q1 to Qm via the resistors R1 to Rm, respectively. Besides, the bases of the transistors are connected with the base of the transistor Qb. The resistor Rr and resistors R1 to Rm have the same resistance value and the transistors Q1 to Qm, Qa and Qb have the same characteristics. Consequently, the reference current control circuit RC and transistors Q1 to Qm compose a current mirror circuit (hereinafter referred to as a current mirror). Thus, a light emission drive current i with the same current value as the reference current IREF is output, flowing between the emitter and collector of each of the transistors Q1 to Qm by mirror effect.
The switch block SB contains m switching elements S1 to Sm which conduct the light emission drive current i outputted from the transistors Q1 to Qm to output terminals X1 to Xm, respectively. In the switch block SB of the first anode line drive circuit 210, the switching elements S1 to Sm are turned on and off separately according to the logical state of the respective first drive data GA1 to GAm supplied from the luminescence control circuit 1′.
For example, when the first drive data GA1 is at logic “0,” the switching element S1 is OFF. On the other hand, when the first drive data GA1 is at logic “1,” the switching element S1 turns on to conduct the light emission drive current i supplied from the transistor Q1 to the output terminal X1. Also, when the first drive data GAm is at logic “0,” the switching element Sm is OFF. On the other hand, when the first drive data GAm is at logic “1,” the switching element Sm turns on to conduct the light emission drive current i supplied from the transistor Qm to the output terminal Xm. In this way, the light emission drive current i outputted from the transistors Q1 to Qm is supplied to the respective anode lines A1 to Am of the ELDP 10′ via the respective output terminals X1 to Xm as shown in FIG. 7.
A pixel drive voltage VBE is applied to the emitter of a transistor Q0 in the control current output circuit CO via a resistor R0. Besides, the base of the transistor Q0 is connected with the base of the transistor Qb in the reference current control circuit RC. The resistor R0 has the same resistance value as the resistor Rr in the reference current control circuit RC. And the transistor Q0 has the same characteristics as the transistors Qa and Qb in the reference current control circuit RC. Consequently, the transistor Q0 in the control current output circuit CO and the reference current control circuit RC compose a current mirror. Thus, the same amount of current as the reference current IREF flows between the collector and emitter of each of the transistor Q0. The control current output circuit CO supplies this current as control current ic to an input terminal Iin of the second anode line drive circuit 22 via an output terminal Iout. In other words, the same current as the light emission drive current i supplied to the anode lines A1 to Am of the ELDP 10′ by the first anode line drive circuit 210 is supplied as the control current ic to the second anode line drive circuit 220.
The second anode line drive circuit 220 comprises a drive current control circuit CC and a switch block SB as well as transistors Q1 to Qm and resistors R1 to Rm serving as m current drive sources. The collector and base of a transistor Qc in the drive current control circuit CC are connected with the input terminal Iin while the emitter is connected to the ground potential via a resistor RQ1. Consequently, the control current ic outputted from the first anode line drive circuit 210 flows between the collector and emitter of the transistor Qc via the input terminal Iin.
The pixel drive voltage VBE is supplied to the emitter of a transistor Qe in the drive current control circuit CC via a resistor RS. Besides, the base and collector of the transistor Qe is connected with the collector of a transistor Qd. The base of the transistor Qd is connected with the collector and base of the transistor Qc while the emitter is connected to the ground potential via a resistor RQ2. The transistors Qc, Qd, and Qe have the same characteristics as the transistor Q0 in the first anode line drive circuit 210 while the resistor RS has the same resistance value as the resistor R0 in the first anode line drive circuit 210. Consequently, the same current as the control current ic outputted from the first anode line drive circuit 210 flows between the collector and emitter of the transistor Qd.
The pixel drive voltage VBE is supplied to the emitters of the transistors Q1 to Qm in the second anode line drive circuit 220 via the resistors R1 to Rm, respectively. Besides, the bases of the transistors are connected with the base of the transistor Qe. The resistor RS and resistors R1 to Rm have the same resistance value and the transistors Q1 to Qm, Qd, and Qe have the same characteristics. Consequently, the drive current control circuit CC and transistors Q1 to Qm compose a current mirror. Thus, the light emission drive current i equal in amount to the control current ic supplied from the first anode line drive circuit 210 is output, flowing between the emitter and collector of each of the transistors Q1 to Qm. The amount of the light emission drive current i outputted from the transistors Q1 to Qm in the second anode line drive circuit 220 is adjusted by the drive current control circuit CC so that it will be equal to that of the light emission drive current outputted from the first anode line drive circuit 210.
The switch block SB contains m switching elements S1 to Sm, which conduct the light emission drive current i outputted from the transistors Q1 to Qm to the output terminals X1 to Xm, respectively. In the switch block SB of the second anode line drive circuit 220, the switching elements S1 to Sm are turned on and off separately according to the logical state of the respective second drive data GB1 to GBm supplied from the luminescence control circuit 1′.
For example, when the second drive data GB1 is at logic “0,” the switching element S1 is OFF. On the other hand, when the second drive data GB1 is at logic “1,” the switching element S1 turns on to conduct the light emission drive current i supplied from the transistor Q1 to the output terminal X1. Also, when the second drive data GBm is at logic “0,” the switching element Sm is OFF. On the other hand, when the second drive data GBm is at logic “1,” the switching element Sm turns on to conduct the light emission drive current i supplied from the transistor Qm to the output terminal Xm. In this way, the light emission drive current i outputted from the transistors Q1 to Qm in the second anode line drive circuit 220 is supplied to the respective anode lines Am+1 to A2m of the ELDP 10′ via the respective output terminals X1 to Xm as shown in FIG. 7.
As described above, with the drive circuit described in the above patent, in addition to the current source (transistors Q1 to Qm) for generating the light emission drive current, the anode line drive circuits contain the drive current control circuit CC for maintaining the amount of the light emission drive current at a level appropriate to inputted control current and the control current output circuit CO for outputting the light emission drive current itself as control current. When the anode lines of a display panel are driven by a plurality of anode line drive circuits each constructed in a separate IC chip, the first anode line drive circuit controls the amount of light emission drive current to be output based on the light emission drive current actually output by the second anode line drive circuit. Thus, even if there are variations in characteristics between the IC chips (serving as the anode line drive circuits), the amounts of light emission drive currents outputted from the individual IC chips will be approximately equal, producing uniform emission luminance on the display panel.
The technique described in the above patent uses a current mirror to transfer the reference current from the first anode line drive circuit 210 consisting of an IC chip to the second anode line drive circuit 220 consisting of another IC chip. Thus, any current variation in the current mirror will cause variation in output current between the IC chips, failing to provide uniform emission luminance on the display panel.
FIG. 10 shows a current mirror composed of N+1 MOS (Metal Oxide Semiconductor) transistors.
As shown in FIG. 10, the current mirror circuit comprises a current source Iorg as well as the N+1 MOS transistors POUT0, POUT1, . . . , and POUTN. Of the N+1 MOS transistors, one MOS transistor POUT0 constitutes a reference current source for the current mirror in conjunction with the current source Iorg. The output currents from the other N MOS transistors are used as drive output for the display panel. In this example, the outputs from the other N MOS transistors POUT1 to POUTN are merged into an output current Iout for use as drive output.
Assume that all the N+1 MOS transistors POUT0 to POUTN have the same size. Then, the current ratio, i.e., the ratio of the current derived by the MOS transistor POUT0 to the current derived by the other N MOS transistors POUT1 to POUTN, is 1:N. The output current Iout at this time is given byIout=N×Iorg
Generally, current variation ΔI depends on the size of MOS transistors. When the size of MOS transistors is small, the current variation ΔI is large. Conversely, when the size of MOS transistors is large, the current variation ΔI is small.
In the case of MOS transistors used to drive display panels, MOS transistors which correspond to the second proportional “N” in the above current ratio “1:N” are far larger in size than the MOS transistor which corresponds to the first proportional “1.” For example, N>10. Thus, the current variation ΔI is mostly attributable to a variation in current generated from the MOS transistor POUT0 which corresponds to the first proportional “1.”
It is also conceivable to reduce the current ratio of the current mirror, for example, to 2:N/2 or 3:N/3. This will reduce the current variation ΔI. However, since there are as many channels as there are anode lines, the amount of current of the current source Iorg must be increased, resulting in increased power consumption of the IC chips.
A current DAC (digital analog converter) circuit is sometimes used as the constant current source for the anode line drive circuit 2 described above. This requires a current DAC circuit with as many channels as there are anode lines. Configuration of such a current DAC circuit is shown in FIG. 11.
The current DAC circuit shown in FIG. 11 can be divided into a BIAS portion B and a DAC portion D. A transistor which acts as the BIAS portion B is connected directly to a reference current source Iref for the current mirror. On the other hand, transistors other than the one which acts as the BIAS portion B operate as a DAC circuit to generate the output current Iout which constitutes a drive signal to be supplied to pixels. This configuration makes it possible to vary data signals (D0 to Dn) sent to the DAC portion D and thereby vary the current mirror ratio and generate the output current Iout which constitutes analog data.
A multi-channel current DAC circuit can be configured to have a plurality of BIAS portions and a plurality of DAC portions or to have a single BIAS portion and a plurality of DAC portions.
A circuit shown in FIG. 12 is configured to have a plurality of BIAS portions and a plurality of DAC portions. Each BIAS portion gives a bias signal to a corresponding DAC portion. In this case, the circuit, in which the BIAS portions and DAC portions are located in close proximity to each other, has the advantage of not being affected by a tendency of Vth in the IC chip or voltage drops due to long wiring.
However, since a current mirror circuit exists on each channel, shifts in drain voltages of transistors will cause systematic shifts in current values. This is because the drain current given by the following equation is shifted slightly by the effect of λ when the drain voltage varies even if the transistors are saturated.IDS=K(VGS−Vth)2·(1+λVDS)Also, random current variation ΔI is generated which depends on transistor size and Von. Thus, this configuration has the disadvantage that the output current Iout of each channel varies. The variation in this case constitutes current variation between adjacent channels.
On the other hand, a circuit shown in FIG. 13 is configured to have a single BIAS portion and a plurality of DAC portions. Thus, the single BIAS portion supplies bias signals to the plurality of DAC portions. In this case since a current mirror circuit is common to all the channels, this configuration can suppress the systematic shift in current value caused by shift in drain voltage of transistors and the random variation ΔI in current values which depend on the size of transistors and Von. This is because the number of times of mirroring is reduced. Thus, this configuration has the advantage that the variation in the output current Iout of each channel is suppressed.
However, the circuit, in which the distance between the BIAS portion and DAC portions varies among channels, has the disadvantage of being affected by a tendency of Vth in the IC chip or voltage drops due to long wiring. The variation in this case constitutes trended variation in output currents in the IC chip.
As described above, each of the circuit configurations in FIGS. 12 and 13 has its own advantages and disadvantages. When adopting a circuit configuration with a single BIAS portion and a plurality of DAC portions and with small variations between adjacent channels as shown in FIG. 13, in particular, it is desired to reduce the trended variation which can occur in the output currents in the IC chip.
A first object of the present invention is to reduce degradation of image quality when constructing anode line drive circuits in a display panel drive circuit from a plurality of IC chips.
A second object of the present invention is to reduce current variation which occurs in a current mirror in anode line drive circuits and eliminate variation in reference voltage among a plurality of IC chips.
A third object of the present invention is to reduce current variation in a display panel drive circuit without increasing power consumption of IC chips.
A fourth object of the present invention is to reduce trended variation in output currents in the IC chip in a display panel drive circuit as well as to reduce variation between adjacent channels by implementing an accurate DAC circuit.